Here are some of the simple verilog codes to practice

Here are some of the simple verilog codes to practice 

 Verilog code for flip-flop with a positive-edge clock.

module flop (clk, d, q);
 input  clk, d;
 output q;
 reg    q;
        
 always @(posedge clk)
 begin
    q <= d;
 end
        endmodule

Verilog code for a flip-flop with a negative-edge clock and asynchronous clear.
 module flop (clk, d, clr, q);
 input  clk, d, clr;
 output q;
 reg    q;
 always @(negedge clk or posedge clr) 
        begin
    if (clr)
       q <= 1’b0;
    else
       q <= d;
 end
        endmodule



Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in and serial out.
 module shift (clk, si, so);
 input        clk,si;
 output       so;
 reg    [7:0] tmp;
 always @(posedge clk)
 begin
    tmp    <= tmp << 1;
    tmp[0] <= si;
 end
    assign so = tmp[7];
        endmodule
        



 Verilog code for a 4-to-1 1-bit MUX using an If statement.
 module mux (a, b, c, d, s, o);
 input        a,b,c,d;
 input  [1:0] s;
 output       o;
 reg          o;
 always @(a or b or c or d or s)
 begin
    if (s == 2’b00)
       o = a;
    else if (s == 2’b01)
       o = b;
    else if (s == 2’b10)
       o = c;
    else
       o = d;
 end
        endmodule



 Verilog Code for a 4-to-1 1-bit MUX using a Case statement.
 module mux (a, b, c, d, s, o);
 input        a, b, c, d;
 input  [1:0] s;
 output       o;
 reg          o;
 always @(a or b or c or d or s)
 begin
    case (s)
       2’b00   : o = a;
       2’b01   : o = b;
       2’b10   : o = c;
       default : o = d;
    endcase
 end
        endmodule