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7 module rom_using_file (
8 address , // Address input
9 data , // Data output
10 read_en , // Read Enable
11 ce // Chip Enable
12 );
13 input [7:0] address;
14 output [7:0] data;
15 input read_en;
16 input ce;
17
18 reg [7:0] mem [0:255] ;
19
20 assign data = (ce && read_en) ? mem[address] : 8'b0;
21
22 initial begin
23 $readmemb("memory.list", mem); // memory_list is memory file
24 end
25
26 endmodule
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7 module rom_using_case (
8 address , // Address input
9 data , // Data output
10 read_en , // Read Enable
11 ce // Chip Enable
12 );
13 input [3:0] address;
14 output [7:0] data;
15 input read_en;
16 input ce;
17
18 reg [7:0] data ;
19
20 always @ (ce or read_en or address)
21 begin
22 case (address)
23 0 : data = 10;
24 1 : data = 55;
25 2 : data = 244;
26 3 : data = 0;
27 4 : data = 1;
28 5 : data = 8'hff;
29 6 : data = 8'h11;
30 7 : data = 8'h1;
31 8 : data = 8'h10;
32 9 : data = 8'h0;
33 10 : data = 8'h10;
34 11 : data = 8'h15;
35 12 : data = 8'h60;
36 13 : data = 8'h90;
37 14 : data = 8'h70;
38 15 : data = 8'h90;
39 endcase
40 end
41
42 endmodule
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