Showing posts with label verilog codes. Show all posts
Showing posts with label verilog codes. Show all posts
Thursday, 3 January 2013
ASIC EBOOK
Application-Specific Integrated Circuits - Addison Wesley Michael John Sebastian Smith
https://docs.google.com/file/d/0Bza2pMEd0piweldtWlNFSkYtTWc/edit
Friday, 28 December 2012
ieee papers for project(vlsi & es)
1 A low-power low-noise CMOS analog front-end
IC for portable brain-heart Monitoring applications
Abstract
In this paper, a low power and low noise eight-channel analog front-end (AFE) IC for portable brain-heart monitoring applications is presented. The developed IC features a fully integrated eight-channel design which includes one channel for diffuse optical tomography (DOT), three channels for electrocardiography (ECG), and four channels for electroencephalography (EEG). In order to achieve the targets of lower power, lower noise, and more efficient area utilization, a new programmable readout channel is invented which is composed of a chopper-stabilized differential difference amplifier (CHDDA), an adjustable gain amplifier, and an adjustable low pass filter (LPF). Furthermore, a 10-bit successive approximation register analog-to-digital converter (SAR-ADC) is employed in conjunction with an analog multiplexer to select a particular biosignal for analog-to-digital conversion. The proposed IC has been fabricated in the TSMC 0.18 um CMOS technology and simulated using HSPICE under a 1.8-V supply voltage and an operating frequency of 512 Hz. The power supply rejection ratio (PSRR) +/- of the CHDDA is 113/105 dB. The power consumption of the programmable readout channel and the SAR-ADC is about 71.159 μW and 8.27 μW, respectively. The total power consumption of the full AFE chip is about 506.38 μW and the chip area is about 1733 × 1733 um2.
ieee papers for project(vlsi & es)
A
Novel Design and Simulation of a Compact and Ultra Fast CNTFET Multi-valued
Inverter Using HSPICE
Abstract
This paper presents a novel design of a
compact multi-valued inverter circuit using Carbon Nanotube Field effect
Transistor (CNTFET). All simulations are done by using HSPICE
model of CNTFET. The novelty of this paper is by using only one circuit all
multi-valued output can be achieved than using three different CNTFET circuits
or complex band-gap reference circuits to produce each reference voltage for
precise output in case of CMOS implementation which are previously done. Also
the same design implementation using MOSFETs with different threshold mask
would increase higher process cost. It is widely considered that CNTFET
possesses high fabrication feasibility and superior device performance than
MOSFET. The extensive simulated results and performance bench-marking of the proposed
design also show a significant reduction in power
delay product (PDP) which aids over 50% faster speed than typical multi-valued
inverter. Hence with this uniquely new design it is possible to accomplish
simplicity, energy efficiency and of course reducing the chip area in modern
ultra low power VLSI circuits.
Paper Link : http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6205527&contentType=Conference+Publications&ranges%3D2011_2012_p_Publication_Year%26matchBoolean%3Dtrue%26searchField%3DSearch_All%26queryText%3D%28%28%28VLSI%29+AND+Low+power%29+AND+hspice%29
Abstract
This paper presents a novel design of a
compact multi-valued inverter circuit using Carbon Nanotube Field effect
Transistor (CNTFET). All simulations are done by using HSPICE
model of CNTFET. The novelty of this paper is by using only one circuit all
multi-valued output can be achieved than using three different CNTFET circuits
or complex band-gap reference circuits to produce each reference voltage for
precise output in case of CMOS implementation which are previously done. Also
the same design implementation using MOSFETs with different threshold mask
would increase higher process cost. It is widely considered that CNTFET
possesses high fabrication feasibility and superior device performance than
MOSFET. The extensive simulated results and performance bench-marking of the proposed
design also show a significant reduction in power
delay product (PDP) which aids over 50% faster speed than typical multi-valued
inverter. Hence with this uniquely new design it is possible to accomplish
simplicity, energy efficiency and of course reducing the chip area in modern
ultra low power VLSI circuits.Paper Link : http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6205527&contentType=Conference+Publications&ranges%3D2011_2012_p_Publication_Year%26matchBoolean%3Dtrue%26searchField%3DSearch_All%26queryText%3D%28%28%28VLSI%29+AND+Low+power%29+AND+hspice%29
Thursday, 27 December 2012
Wednesday, 26 December 2012
memory reading codes
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