ieee papers for project(vlsi & es)

1     A low-power low-noise CMOS analog front-end IC for portable brain-heart Monitoring applications

Abstract

In this paper, a low power and low noise eight-channel analog front-end (AFE) IC for portable brain-heart monitoring applications is presented. The developed IC features a fully integrated eight-channel design which includes one channel for diffuse optical tomography (DOT), three channels for electrocardiography (ECG), and four channels for electroencephalography (EEG). In order to achieve the targets of lower power, lower noise, and more efficient area utilization, a new programmable readout channel is invented which is composed of a chopper-stabilized differential difference amplifier (CHDDA), an adjustable gain amplifier, and an adjustable low pass filter (LPF). Furthermore, a 10-bit successive approximation register analog-to-digital converter (SAR-ADC) is employed in conjunction with an analog multiplexer to select a particular biosignal for analog-to-digital conversion. The proposed IC has been fabricated in the TSMC 0.18 um CMOS technology and simulated using HSPICE under a 1.8-V supply voltage and an operating frequency of 512 Hz. The power supply rejection ratio (PSRR) +/- of the CHDDA is 113/105 dB. The power consumption of the programmable readout channel and the SAR-ADC is about 71.159 μW and 8.27 μW, respectively. The total power consumption of the full AFE chip is about 506.38 μW and the chip area is about 1733 × 1733 um².

           Paper Link :                    http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5754151&contentType=Conference+Publications&ranges%3D2011_2012_p_Publication_Year%26matchBoolean%3Dtrue%26searchField%3DSearch_All%26queryText%3D%28%28hspice%29+AND+Low+power%29